1. Field of the Invention
This invention relates to switching circuitry and, more particularly, to a self-routing switching device and concomitant methodology that accommodate packets of different lengths.
2. Description of the Background Art
A modem packet switch, including an IP (Internet Protocol) router, should efficaciously handle the integrated traffic generated by both narrow-band and broadband communication services. Real-time voice communications account for the bulk of narrow-band traffic and require small packet sizes to minimize packetization delay. Broadband communications, on the other hand, prefer large packet sizes in order to minimize the cost incurred in the per-packet overhead.
Uniform packetization of the mixed traffic, that is, restricting packets to the same length regardless of traffic, results in inefficiency, with the ATM (Asynchronous Transfer Mode) cell being a prominent example. However, it is generally true that a uniform packet size greatly simplifies the design of broadband switching fabrics and, thereby, somewhat enhances the switching efficiency. A notable example is “self-route switching” of uniform packets, where the switching fabric is constructed from the interconnection of primitive switching elements and the switching control of each element is by just the so-called “in-band” control signals carried by the input packets to this element (as discussed in more detail shortly). The extremely distributed nature of the switching control in this manner allows for the construction of a large broadband switching fabric from massive integration of most primitive switching elements, typically 2×2 elements.
The circuitry shown in FIG. 1 is representative of a typical, conventional 2×2 self-routing switching element 100. With reference to packet “frame” 201 shown in FIG. 2, wherein packet 205 having header 206 and payload 207 is shown as being representative of a packet communicated during time frame 201, the construction and operation of element 100 is as follows. In packet time frame 201, an independent packet represented by the form of packet 205, enters input port 101-1 (Input 0) and, concurrently, another packet enters input port 101-2 (Input 1) of the 2×2 element as serially propagated bits, that is, bit pipelined. The beginning bit(s) of each packet constitutes an “in-band” control signal, and is typically conveyed by header 206. Payload 207 conveys the actual data, that is, non-control data, communicated by packet 205. The two in-band control signals in the separate headers enter shift registers 102-1 and 102-2, respectively, associated with their respective input ports.
The “connection state” of switching element 100 may be broadly construed as the manner in which Input 0 and Input 1 are coupled to Output 0 and Output 1 in a given time frame. For instance, an exemplary connection state is one whereby Input 0 is connected to Output 1 and, concurrently, Input 1 is connected to Output 0 (such a connection state is oftentimes referred to as the “cross-state” of a 2×2 element). The selection of the connection state of switching element 100 is controlled by connection state circuitry 105 inside control section 103 of element 100. The connection state of element 100 is arbitrary at the beginning of each frame time (e.g., the connection state may be the connection state remaining at the completion of a previous frame). Thus, the connection state circuitry 105 uses the two in-band control signals provided by shift registers 102-1 and 102-2, respectively, to select a connection state. In particular, the connection state specifies which input (Input 0 or Input 1) is to be connected to Output 0, and more explicitly, which shift register (102-1 or 102-2) may feed its data into the multiplexer (or mux) 104-1 associated with Output 0; similarly, the connection state also specifies which input (Input 0 or Input 1) is to be connected to Output 1, and more explicitly, which shift register (102-1 or 102-2) may feed its data into the multiplexer (or mux) 104-2 associated with Output 1. Note that it is possible for an input to couple to more than one output. The operation of the connection state circuitry 105 is aided by two memory registers: the clock counter 106 and the latch status 109.
Thus, the in-band control signal indicates whether its packet is an idle expression and, for a non-idle packet, the intended output port(s) of the packet plus auxiliary information such as the priority class of the packet. The selection of the connection state attempts to route each of the two incoming packets to the intended output port(s) by the content of their in-band control signals. But, in case of a contention situation, e.g., when both incoming packets are of the same priority class and intended for the same output port, the selection of the connection state needs to resolve the contention by, for example, misrouting or blocking one of the two packets. On the other hand, when a packet is merely an idle expression, it is optional for the connection state to route the idle expression to an idle output.
In order to relate conventional self-routing switching to the invention described in the sequel, it is assumed that a connection state always connects each of the two outputs to an input. Thus, when the winner packet in the contention occupies only one of the two outputs, the loser packet is misrouted to the unoccupied output. Similarly, an idle expression is routed to some output unless a non-idle packet occupies both outputs.
As soon as the connection state is selected, it is “latched”, that is, maintained throughout the duration of the flow of bits (both header and payload) in the packet, and will be unlatched at beginning of the next packet frame time. Latch status 109 may, for example, be a 1-bit register that keeps track of latching. Clock counter 106 is reset by the signal from frame clock 107; frame boundary markers (e.g., short duration pulses) for frame 201 and the next succeeding frame are shown by signals 210-1 and 210-2, whereby signal 201-1 indicates the start of the current frame 201, and signal 210-2 shows the start of the next frame. Clock counter 106 is incremented and progresses upon every signal from the bit clock 108 based upon the bit-rate of the incoming bits comprising a packet. Corresponding to each value of clock counter 106, control section 103 prescribes commands to control the two shift registers and the two multiplexers. Frame clock 107 and bit clock 108 are derived in any conventional manner from the incoming packet stream—for example, from synchronization circuitry (which is not shown because it is conventional) which determines frame clock 107 and bit clock 108.
Packet 205 of FIG. 2 illustrates the typical format of a packet. A packet may traverse through many primitive switching elements such as element 100 inside a self-routing switching fabric, and its in-band control signal for different switching elements on its route may be different. Upon entering the switching fabric, the header 206 of the packet must contain enough information to conveniently derive the in-band control signal for every switching element on the route. Upon entering each switching element, the in-band control signal needs to occupy a certain fixed bit position(s) at the front or near the front of the packet. Upon exiting the switching element, the same bit position(s) must be occupied by the in-band control signal for the next switching element on the route. Thus, each switching element on the route of the packet may make some quick change to the front bits of the packet. For example, the switching element may consume the leading bit of the packet.
Primitive switching element 100 exemplified by the above description of FIG. 1 functions only for packets of a uniform size. The prior art is devoid of a self-routing switching mechanism that accommodates packets of different lengths at a minimal additional cost to the hardware.